Dreamcast audio hardware
Sound on the Dreamcast is a separate computer inside the console: a Yamaha AICA chip with its own CPU, memory, voices and effects processor. The main CPU only reaches it over a slow side bus.
Two computers, one sound system
Hitachi SH-4, 200 MHz
Runs the game. Sound is a library call away: Sega's sd sound library (Soul Calibur links version
1.00.18) turns calls like sdMidiPlay or sdPstmPlay into small command
records, uploads sound data, and polls status. The SH-4 cannot play a note itself; everything audible
happens in the AICA.
Yamaha AICA
A complete sound subsystem on one chip: an ARM7DI CPU, a 64-channel sample player, an effects DSP, a mixer and DAC interface, three timers, an interrupt controller and a MIDI UART, all built around 2 MB of sound RAM. The ARM runs whatever program the SH-4 loads into that RAM: for most games built on Sega's SDK, that is the Manatee sound driver.
Holly and the G2 bus
The SH-4 does not have a direct wire to the AICA. It reaches it through Holly, the system ASIC that also contains the PowerVR graphics core. Holly bridges the SH-4's bus to the G2 bus, a slow peripheral bus shared with the modem and the expansion port.
- Everything is memory-mapped. From the SH-4, the AICA's registers appear at
0x00700000and sound RAM at0x00800000(normally accessed uncached, through the0xA0xxxxxxmirror). - It is slow. Each access crosses the bridge and competes with the AICA's own use of sound RAM. Software must respect the G2 write FIFO before writing (Sega's library wraps every access in helpers that do this).
- Bulk copies use DMA. Holly has G2 DMA channels that copy main RAM to sound RAM without the CPU; the sd library uses them (or plain CPU copies) to upload banks, stream data and the command mailbox.
- Interrupts from the AICA to the SH-4 are routed through Holly's interrupt controller.
Inside the AICA
The ARM7DI
The sound CPU is an ARM7DI, an early ARM core implementing the ARMv3 architecture. Compared with later ARM7s it has no Thumb instruction set and no halfword load/store instructions, which is visible in the driver: 16-bit values are assembled from bytes or extracted with shifts. Its nominal clock is about 22.6 MHz, but it fetches every instruction from the same sound RAM that 64 voices and the DSP are reading at audio rate, so its real throughput is a fraction of that. A few consequences shape the whole driver:
- Everything is table driven. Pitch, pan and level conversions are table lookups rather than maths.
- Work is batched on a 4 ms tick. Fades, sequencing and parameter updates happen 250 times a second, not per sample.
- The chip does the audio. The ARM never touches a sample: it only programs registers. The sound generator and DSP do all real-time signal processing.
The SH-4 controls the ARM's reset line (a bit in the AICA's control register): the ARM is held in reset while its program is being uploaded, then released. When released it starts executing at address 0 of sound RAM, the ARM reset vector.
Registers
Everything in the AICA is controlled through a 64 KB block of memory-mapped registers:
| Block | What it controls |
|---|---|
| Channel registers | 64 blocks of 128 bytes, one per voice: sample address and format, loop points, envelope rates, pitch, LFO, sends, pan, level, filter levels and rates, key on/off. |
| Common registers | Master volume and mono/stereo, the DSP ring-buffer location, the MIDI port, the channel monitor, DMA, the three timers, the two interrupt controllers, ARM reset. |
| DSP output mixer | Level and pan for each of the 16 DSP outputs and the 2 external (CD) inputs. |
| DSP program | Coefficients, memory addresses, the 128-step microprogram and the DSP's working registers. |
Two views of the same memory
Sound RAM and the AICA registers are visible to both CPUs, at different addresses. This shared view is the entire communication channel between the game and the driver.
0x00813200 is read by the ARM at 0x00013200.Timers and the interrupt controller
The AICA has one interrupt controller with two "customers":
- The ARM. About eleven sources (external pins, MIDI in, DMA done, "the SH-4 poked me", timers A/B/C, MIDI out, and a per-sample tick) each have an enable, a pending and a reset bit. Every source is also assigned a priority level from 0 to 7. When an enabled source fires, the ARM's FIQ (fast interrupt) line is raised and a register reports the level of the source, so the handler can jump straight to the right code.
- The SH-4. A parallel set of enable/pending/reset bits raises an interrupt towards the main CPU, delivered through Holly.
The three timers count output samples (44,100 per second), optionally divided by a power of two, and interrupt when they overflow. That makes them ideal for musical timing: they are locked to the audio clock. The Manatee driver uses Timer A for its heartbeat; see SH-4 ↔ ARM communication for exactly how.
On ARM, FIQ has its own banked copies of registers r8-r14, so a FIQ handler can do real work without saving anything. The AICA only wires up FIQ (the normal IRQ line is never raised), so every interrupt the driver receives arrives as a FIQ.
CD audio
The GD-ROM drive can play Red Book audio tracks. Their samples are delivered digitally to the AICA's two external inputs, which pass through the DSP input stage and the output mixer like any other source. The driver exposes their volume and pan as "GD-DA" host commands, but otherwise leaves them alone.